The present invention relates to contents addressable memories. In particular although not exclusively the invention relates to contents addressable memories for use as fully associative cache memories.
Cache memories may be characterised by the number of cache locations into which a particular block of data may be placed. For example, if a block of data called up from main storage may be placed in any of four separate locations in a cache memory then the cache is said to be four way set associative. Caches may range from one way set associative, or direct-mapped caches, to fully associative, in which a block of dam may be placed in any location.
Each location in a cache memory comprises an address store location and an associated data store location. When a processor served by the cache memory issues a new address, the cache compares this address with any addresses it holds in its address store locations, and if the new address matches that held in one of the address store locations the data held in the associated store location is passed to the processor. In a direct mapped cache in which only one location can possibly hold the required data only one comparison is required. As the level of associativity increases so does the number of comparisons required, and since these comparisons must be done in parallel to meet the timing constraints imposed by the processor, this requires the use of a contents addressable memory.